A semiconductor chip can generate or receive a high-speed I/O signal at an input or output (I/O) cell and may conduct the signal to or from a package terminal. The high-speed I/O signals may travel on transmission lines that are intended to maintain signal fidelity over a distance. The I/O cell may be a group of integrated active and passive elements. The package terminal may couple the semiconductor chip to external devices.
The semiconductor chip I/O cell may couple the high-speed I/O signal to a differential pair based transmission line, a single-ended transmission line, or a waveguide. A differential pair based transmission line may include one or more ground planes. A single-ended transmission line can refer the high-speed I/O signal to a ground plane.
The differential pair has a proximal and a distal end that can couple to the I/O cell and one or more package terminals, respectively. For example, a transmission line can couple a signal from the I/O cell to a solderable package pin, a flat lead, a J-lead, an S-lead, or a solder ball in a ball grid array (BGA) package. The transmission line may be interrupted by a routing via, such as a package via, a blind via, a buried via, and the like, and may be terminated at either end by resistances, capacitances, and reactances that impose impedance discontinuities. For example, a capacitive discontinuity may occur at either end of a package trace. A capacitance discontinuity together with the length of a trace may limit signal transmission. For example, both the I/O cell and the package-to-board coupling element or linkage may have some parasitic capacitance. Accordingly, the capacitive discontinuities at either end of the trace may be a result of the I/O cell being characterized by some amount of parasitic capacitance and the package linkage to the board, such as a BGA ball, being also characterized by some amount of capacitance.